Design engineering has advanced by leaps and bounds with the effort by semiconductor vendors supporting development of special purpose software and development of new firmware in operating systems. Even before the availability of ASICs (application specific integrated circuits), design engineers spared no effort in building prototype boards and to enable software engineers to build required codes and make innovations in how to use available resources efficiently. Another available tool for design engineers comprises hardware accelerators which have been used profusely to speed design and simulation work. With designs getting larger and more complex, there is now added impetus to use the SoC (system-on-a-Chip) approach to cater to increasing design needs and demands. Compelling advantages in terms of cost and flexibility offered by SoC solutions, that pack a DSP with multiple minimally programmable coprocessors or hardware accelerators under the control of that DSP, have made such SoCs very popular. Real time multimedia processing, which usually involves sequential data dependencies, poses technical challenges in realizing the design on such a multi-processor architecture owing to shared resource limitations (such as on-chip memory, DMA controller) and variations in the processing complexity from one processing stage to the other. In design efforts involving especially multimedia processing, where multiple co-processors and or hardware accelerators are used, there is a need to ensure that an efficient and flexible use of the resources is made in terms of the allocation of processing tasks and the time taken to complete the allocated tasks.